CSE 600 (Ongoing Research Seminar)

David Patterson joined the faculty at the University of California at Berkeley in 1977, where he now holds the Pardee Chair of Computer Science. He is a member of the National Academy of Engineering and is a fellow of both the ACM (Association for Computing Machinery) and the IEEE (Institute of Electrical and Electronics Engineers).

He led the design and implementation of RISC I, likely the first VLSI Reduced Instruction Set Computer. This research became the foundation of the SPARC architecture, used by Sun Microsystems and others. He was a leader, along with Randy Katz, of the Redundant Arrays of Inexpensive Disks project (or RAID), which led to reliable storage systems from many companies. He is co-author of five books, including two with John Hennessy, who is now President of Stanford University. Patterson has been chair of the CS division at Berkeley, the ACM SIG in computer architecture, and the Computing Research Association.

His teaching has been honored by the ACM, the IEEE, and the University of California. Patterson shared the 1999 IEEE Reynold Johnson Information Storage Award with Randy Katz for the development of RAID and shared the 2000 IEEE von Neumann medal with John Hennessy for "creating a revolution in computer architecture through their exploration, popularization, and commercialization of architectural innovations."

It is time to broaden our performance-dominated research agenda. A four order of magnitude increase in performance over 20 years means that few outside the CS&E research community believe that speed is the only problem of computer hardware and software. If we don't change our ways, our legacy may be cheap, fast, and flaky. Recovery Oriented Computing (ROC) takes the perspective that hardware faults, software bugs, and operator errors are facts to be coped with, not problems to be solved. By concentrating on Mean Time to Repair rather than Mean Time to Failure, ROC reduces recovery time and thus offers higher availability. Since a large portion of system administration is dealing with failures, ROC may also reduce total cost of ownership. ROC principles include design for fast recovery, extensive error detection and diagnosis, systematic error insertion to test emergency systems, and recovery benchmarks to measure progress. If we embrace availability and maintainability, systems of the future may compete on recovery performance rather than just processor performance, and on total cost of ownership rather than just system price. Such a change may restore our pride in the systems we craft.

Pat Hanrahan is the CANON USA Professor of Computer Science and Electrical Engineering at Stanford University where he teaches computer graphics. His current research involves visualization, image synthesis, and graphics systems and architectures. Before joining Stanford he was a faculty member at Princeton. He has also worked at Pixar where he developed developed volume rendering software and was the chief architect of the RenderMan(TM) Interface - a protocol that allows modeling programs to describe scenes to high quality rendering programs. Previous to Pixar he directed the 3D computer graphics group in the Computer Graphics Laboratory at New York Institute of Technology. Professor Hanrahan has received three university teaching awards. He has received an Academy Award for Science and Technology, the Spirit of America Creativity Award, the SIGGRAPH Computer Graphics Achievement Award, and was recently elected to the National Academy of Engineering.

Recently NVIDIA has claimed that their graphics processors (or GPUs) are improving at a rate three times faster than Moore's Law for processors. A $25 GPU is rated from 50-100 gigaflops and approximately 1 teraop (8-bit ops). Alongside this increase in performance is new functionality. The most recent innovation is user-programmable vertex and fragment stages that allow GPUs to compute a wide range of new visual effects enabling movie-quality games. Announced chips have as many as 200 programmable floating point units operating in parallel. The result is that the latest generation of commodity graphics and game chips are powerful data-parallel computers. Why are these graphics processors so fast? Will the future performance of GPUs continue to increase faster than CPUs? And, if so, what are the implications for computing?

Amanda Stent received her PhD in computer science from the University of Rochester, where she worked with James Allen on the TRIPS dialogue system. She has been on the faculty in the CS department at Stony Brook since January 2002.  Her areas of research interest include:  natural language and multimodal generation for dialogue, spoken dialogue systems, theories of discourse, and multimedia information extraction.