CSE 635

CSE 653: Seminar in Concurrency, Spring 2002
Focus Area: Embedded Systems.

[Announcements]

Instructor: Radu Grosu ( grosu At cs DOT sunysb DOT edu),

Class: Thu 1pm - 3pm, CS Building, room 1441

Office hours: TueThu 10-11am, CS Building room 1425, and by appointment

Overview
Reading
Tentative schedule

Overview

Embedded systems are becoming an integral part of nearly every engineered product: they control consumer products, commercial aircraft, nuclear power plants, medical devices, weapon systems, aerospace systems, automobiles, public transportation systems, and so on. At the same time quality and confidence issues are increasing in importance. Errors may result in loss of life, destruction of property, failure of businesses, and environmental harm. Today, designers check that an embedded system works properly by using simulation and testing. However, as embedde systems become more complex and pervasive, these traditional techniques are not sufficient to assure desired reliability. New computer-aided verification techniques are emerging as practical alternatives. They allow the designer to verify that a mathematical model of a system satisfies its abstract logical specification. This approach has been most effective for control-intensive components, and is rapidly becoming an integral part of the design cycle in many companies.

In this seminar course/reading group, we will read several papers on design and computer-aided verification of embedded systems. We expect to cover the following subtopics:

synchronous languages

Esterel
VHDL
Statecharts
Hierarchic Reactive machines
Petri Nets

hardware/software codesign

compilers for DSP
compilers for FPGA (emulation)
hardware/software verification
partitioning, scheduling

hybrid (mixed analog/digital) systems

VHDL-AMS
hybrid hierarchic machines
mixed-signal synthesis
hybrid systems simulation
hybrid systems verification

Other areas and/or papers will be selected, based on participant interest. A preliminary list of papers is given below. Every student participating in the reading group will be expected to present one paper during the course of the semester, and to engage actively in dicussions. Students can register formally for the CSE 653 course for one credit, or attend the meetings without registration.

Reading

A preliminary list of papers is given below. Other areas and/or papers will be selected, based on participant interest. Every student participating in the reading group will be expected to present one paper during the course of the semester, and to engage actively in dicussions.

Overview

Design of embedded systems: formal models, validation, and synthesis, S. Edwards, L. Lavagno, E.A. Lee, and A. Sangiovanni-Vincentelli. Proceedings of the IEEE, 85(3):366--390, March 1997.
Formal Models for Embedded System Design, Marco Sgroi, Luciano Lavagno, Alberto Sangiovanni-Vincentelli. IEEE Design & Test of Computers, 17, 2, 14-27, June, 2000

Synchronous languages

The VHDL Cookbook, P.J. Ashenden
Handbook on Verilog HDL, D.C. Hyde
The IEEE Verilog 1364-2001 Standard. What's New and Why You Need It, S. Sutherland
The Foundations of Esterel, G. Berry. In Proof, Language and Interaction: Essays in Honour of Robin Milner, G. Plotkin, C. Stirling and M. Tofte, editors, MIT Press, Foundations of Computing Series, 2000 .
The Synchronous Programming Language ESTEREL: Design, Semantics, Implementation,, G. Berry and G. Gonthier. Sience of Computer Programming, 19 (1992) 87-152.
Statecharts, a Visual Formalism for Complex Systems, D. Harel. Sience of Computer Programming, 8 (1992) 231-274.
Modular Refinement of Hierarchic Reactive Machines, R. Alur, R. Grosu. In Proc. of POPL'00, Boston, Massachusetts, January 19-21, 2000

Hardware/software codesign

Software Synthesis and Code Generation for Signal Processing Systems, S. Bhattacharyya, R. Leupers, P. Marwedel, IEEE Trans. on Circuits and Systems, 47(9),2000

Power Analysis and Minimization Techniques for Embedded DSP Software, M.T. Lee, V. Tiwari, S. Malik, M. Fujita. IEEE Trans. on VLSI, 9(1), 1997
Hardware/Software Codesing and Rapid Prototyping of Embedded Systems, F. Slomka, M. Dorfel, R. Munzenberger, R. Hoffmann. IEEE Design & Test of Computers
The Extended Partitioning Problem: Hardware/Software Mapping, Scheduling and Implementation Selection, A. Kalavade, E.A. Lee.Design Automation
Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems, A. Doboli, P. Eles. Proceedings of the ICCD'98, IEEE CS Press,1998.
Synthesis of Embedded Software from Synchronous Dataflow Specifications, S. Bhattacharyya, P.K. Murthy, E.A. Lee,Journal of VLSI SP 21, 1999

Hybrid (mixed analog/digital) systems

Using top-down CAD toolds for mixed analog/digital ASICs: a practical design case, S. Donnay, G. Gielen, W. Sansen, W. Kruiskamp, D. Leenaerts, S. Buytaert, K. Marent, M. Buckens, C. Das. Kluwer international journal on Analog Integrated Circuits and Signal Processing, Vol. 10, No. 1/2, pp. 101-117, June-July 1996.
VHDL-AMS--A Hardware Description Language for Analog and Mixed-Signal Applications, E. Christen and K. Bakalar. IEEE Trans on Circuits Systems, 46(10), 1999
Compositional Refinement for Hierarchical Hybrid Systems, R. Alur, R. Grosu, I. Lee, O. Sokolsky. In Proc. of HSCC'01, Rome, Italy, March 23-25, 2001.
Behavioral Synthesis of Analog Systems using Two-Layered Design Space Exploration, A. Doboli et al. Proceedings of the 36th DAC, 1999.
Optimal Design of a CMOS OP-Amp via Geometric Programming, M.d.M. Hershenson, S.P. Boyd. IEEE Trans on CAD of ICS, 20(1), 2000

Tentative Schedule

No	Date	Topic	Lecturer
1.	Jan 31	Organizational meeting.	Radu Grosu
2.	Feb 07	Introduction to Embedded Systems	Radu Grosu
3.	Feb 14	Design of embedded systems: formal models, validation, and synthesis, S. Edwards, L. Lavagno, E.A. Lee, and A. Vicentelli	Radu Grosu
4.	Feb 21	The Synchronous Programming Language ESTEREL: Design, Semantics, Implementation,, G. Berry and G. Gonthier.	Radu Grosu
5.	Feb 28	Handbook on Verilog HDL, D.C. Hyde	Rohit Pai
6.	Mar 07	The VHDL Cookbook, P.J. Ashenden	Ashish Shah
7.	Mar 14	Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems, A. Doboli, P. Eles	Alexa Doboli
8.	Mar 21	Power Analysis and Minimization Techniques for Embedded DSP Software, M.T. Lee, V. Tiwari, S. Malik, M. Fujita	Jyoti Wagolikar
***	Mar 28	Spring recess (no class)
9.	Apr 04	Statecharts, a Visual Formalism for Complex Systems, D. Harel.	Paloma Mukherjee
10.	Apr 11	Synthesis of Embedded Software from Synchronous Dataflow Specifications, S. Bhattacharyya, P.K. Murthy, E.A. Lee	Vaishali Wani
11.	Apr 18	Hardware/Software Codesing and Rapid Prototyping of Embedded Systems, F. Slomka, M. Dorfel, R. Munzenberger,	Nat
12.	Apr 25	Modular Refinement of Hierarchic Reactive Machines, R. Alur, R. Grosu.	Qinghua Zhang
13.	May 02	VHDL-AMS, IEEE Standard 2001	Harshad Kamat
14.	May 09

Last updated on Apr 11, 2002 by Radu Grosu