CSE 220: Systems Fundamentals I – Course Schedule (Sections 1 & 2)

Lecture Section L01 (Wong): Mondays & Wednesdays, 8:30 - 9:50 am in Melville Library W4525

Lecture Section L02 (Wong): Tuesdays & Thursdays, 2:30 - 3:50 pm in ENG 145

The following course schedule schedule is tentative and subject to change. Readings are taken from Digital Design and Computer Architecture, 2nd edition by David Money Harris and Sarah L. Harris. You will gain more from lecture if you complete the readings before coming to class. The answers to the suggested textbook exercises can be downloaded here. Note that only odd-numbered exercise solutions are available.

Week of Lecture Topics Wong Notes Readings Textbook Exercises &
Other Resources
1/22
  • Unit 0: Course Overview
  • Unit 1: Introduction to Digital Systems and von Neumann Architecture
  • Secs. 1.1-1.3
 
 
  • Unit 2: Number Systems
  • Secs. 1.4
 1/29
  • Unit 3: MIPS Assembly: Basic Instructions, System Calls, Endianness, Machine Language
  • Secs. 6.1-6.4.4
 

  • Unit 3: MIPS Assembly: Basic Instructions, System Calls, Endianness, Machine Language (cont.)
  • Secs. 6.1-6.4.4
 2/5
  • Unit 4: MIPS Assembly: Branches and Loops
  • Secs. 6.1-6.4.4

  • Unit 4: MIPS Assembly: Branches and Loops
  • Secs. 6.1-6.4.4
 
2/12
  • Unit 5: MIPS Assembly: Function Calls and the Stack
  • Sec. 6.4.6

  • Unit 6 and 7: MIPS Assembly: Single-dimensional Arrays, Memory Alignment, Multi-Dimensional Arrays
  • Sec. 6.4.5
 2/19
  • Unit 8: Logic Gates; Digital Logic Design: Boolean Equations and Algebra
  • Secs. 1.5, 2.1-2.4
  • Exer. 1.71-1.75 (odds), 2.1-2.25 (odds)
  • Unit 8: Logic Gates; Digital Logic Design: Boolean Equations and Algebra (cont.)
2/26
  • Unit 9: Digital Logic Design: Multilevel Combinational Logic
  • Secs. 2.5
  • Exer. 2.27-2.37 (odds)

  • Unit 10: Digital Logic Design: kmaps
   
 3/5
  • Unit 11: Digital Logic Design: Combinational Building Blocks and Timing
  • Secs. 2.8, 2.9
  • Exer. 2.39-2.47 (odds)
Midterm
  • Midterm Exam: Wednesday, March 7 at 8:45 pm in location TBD

  • Unit 11: Digital Logic Design: Combinational Building Blocks and Timing (cont.)
  • MIDTERM
  • Secs. 2.8, 2.9
 
3/12
  • SPRING BREAK  - NO LECTURE

  • SPRING BREAK  - NO LECTURE
 3/19
  • Unit 12: Digital Logic Design: Arithmetic Circuits
  • Sec. 5.2
 

  • Unit 12: Digital Logic Design: Arithmetic Circuits (cont.)
  • Sec. 5.2
 3/26
  • Unit 12: Digital Logic Design: Arithmetic Circuits (cont.)

  • Unit 13: MIPS Architecture: Single-Cycle Processors
  • Secs. 7.1-7.3
  • Exer. 7.1-7.7 (odds)
 4/2
  • Unit 13: MIPS Architecture: Single-Cycle Processors (cont.)
  • Secs. 7.1-7.3
 

  • Unit 13: MIPS Architecture: Single-Cycle Processors (cont.)
  • Sec. 7.4
  • Exer. 7.9, 7.13, 7.15-7.19 (odds)
 4/9
  • Unit 14: MIPS Architecture: Multicycle Processors
  • Sec. 7.4
 

  • Unit 14: MIPS Architecture: Multicycle Processors (cont.)
  • Sec. 3.3-3.4, 7.4
 
 4/16
  • Unit 14: MIPS Architecture: Multicycle Processors (cont.)
  • Sec. 7.5
 

  • Unit 15: MIPS Architecture: Pipelined Processors
  • Sec. 7.5
 
4/23
  • Unit 15: MIPS Architecture: Pipelined Processors (cont.)
  • Sec. 7.5
 
 
  • NO LECTURE
4/30
  • Unit 15: MIPS Architecture: Pipelined Processors (cont.)
 
 
  • Unit 15: MIPS Architecture: Pipelined Processors (cont.)
   
Final
  • Final Exam: Wednesday, May 16 from 8:00 am - 10:45 am